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| Bug 01 |
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Fault:	
	BC Register pair overflow

Description:
	Found during simulation, The BC register pair will keep decrementing after reaching 0 in the ONE_SEC loop
	The program never sets the zero flag on the processor when the BC register pair hits zero
	Maybe the accumulator needs to be used instead?

Actions:
	Added LD A, 0h before RET instruction in MILLISEC to manually load a zero into the accumulator.
	No change in execution. BC register pair will still overflow to FF

	Added LD A, B && LD A, C && JP NZ, ONE_SEC to ONE_SEC loop
	Trying to force the machine to read a correct zero flag from accumulator
	Did not work. Continues execution without setting zero flag

	Added XOR A && ADD A, B && ADD A, C to set zero flag using addition
	Now working

Resolution:
	Found using addtion instruction in the accumulator results in the zero flag being set properly
	Recommend using this method for all applicable timing loops.